Error issue see Errata. You need to correct item 1

PCB must have the following modifications carried out during assembly:

• cut the short track between R6 and C401
• strap the output of Attenuator 2 (5dB) to the SJ901 pad input to the multiplier
• strap the output of the multiplier (SJ902) to C401
• it is recommended that a diplexer is used after the VHF BPF
• If using S18 inductors, prepare shielding for both of the VHF BPF's - for L205/206, use a piece of hobby brass 67mm x 17mm. Fold each end in at 17.5mm. Cut a screen to fit centrally between the two coils. For L601/602, the procedure is identical - but the screen is 61mm long before bending.

The 108.667MHz version requires:

• the diode multiplier (Sheet 2),
• Logic Stages with 1 divider(IC402) - both inverter packages (IC401/404) required (Sheet 4)
• 10 to 20MHz doubler and filter, (Sheet 9)
• 1.33MHz low pass filter, (Sheet 9)
• 108.667MHz BPF/diplexer, amplifiers, crystal filter and output LPF(Sheets 6 & 7)

The input buffer circuit (Sheet 1) is required to drive the doubler - note that a 'daisy-chain' 10MHz output is not available with this implementation.

The Input Buffer input attenuator (Atten 1) should be set for 7dB if the drive level available is +10dBm - Adjust the value according to your input signal to obtain +10dBm at the input to the diode multiplier.

The second attenuator (Atten 2 - via the two way splitter after IC1) must be set to 5dB nominally for a +10dBm reference input. If your input is at a different level, adjust the value of this attenuator to give approx +3dBm into the tripler

Set the attenuator following the VHF multiplier chain to give around 0dBm into the mixer RF port - often 3dB is the correct value here.

The attenuator following SJ902 should be set to give a level of approx +6dBm into the mixer LO port.

Divider 1 (IC402) must be set to divide by 15 to give 1.33MHz output - hence the jumpers must be programmed as binary 1 (0001) reading in order DCBA. Jumper C (pin 3, SJ1) must be grounded, the remaining 3 taken to the 10k pull-up resistor, R403

Divider Outputs: Divider 1 output (IC402) is taken from pin 11.

Standard ADE-1 mixer required

Tune each filter onto frequency using a signal generator and power meter or spectrum analyser as you go through the construction. This will ease the final tune up. As you complete each chain, adjust it before the mixer is inserted.

For example, build the 110MHz filter, align it, then build the amplifier stages following. Check and re-align. Build the diode multiplier and test through to output of the amplifiers. Set the attenuator value to give approx +6dBm into the mixer. Build the logic stages and check the output is correct in frequency. Build the 10 to 20 MHz doubler and check/align it. Using a scope, check that there is a nice square wave output from IC401, pin 2 (may be easier to look at IC402 pin2) Check output of divider through LPF - you should see approx +12dBm (>5.5vp-p) of 1.33MHz present. Set the output atten from the LPF to reduce this level down to between 0 and +2dBm< into the mixer./p>

Build the 108.667MHz BPF and align it. Once both outputs are optimised, insert the mixer and check the output through the BPF, optimising if necessary. Follow through with the remaining filters.

Final alignment should be done on a spectrum analyser. Carefully adjust the trimmer capacitors of the crystal filter for minimum spurii, and maximum wanted signal. The adjustments are iterative, and very small movements make significant differences to the output. You may also find it beneficial to make minor adjustments to the 110MHz filter and the 1.33MHz filter to get the best rejection of other products.

Typical results are Wanted output: +8 dBm

Spurii < -65 dBc

Harmonics < -40 dBc

Supply voltage - 13.8V DC

Current drawn - 360 mA

Completed 108.667MHz DFS - topside view	Output Spectrum 0 - 500MHz. Top of scale is +10dBm	Output Spectrum +/-25MHz. Top of scale is +10dBm

Because this DFS implmentation uses widely spaced LO and RF signals at the VHF mixer (M601) it is advantageous to provide a diplexer, to correctly terminate the unwanted products from the mixing process - the image output, and the LO feedthrough. This reduces the levels of spurious components present in the final stages of the DFS circuitry, and also helps to keep the following LO multiplier chain cleaner. On this implementation, there is a noticeable improvement in the spectrum at the LO and image frequencies of the VHF mixer

Page created 19 May 2008

Page last updated 25 Aug 2008